1. Field of the Invention
The present invention relates to central processing units and more particularly to a central processing unit having a register of an expanded size and having addressing capability compatible with an lower-class central processing unit in which a bank register is used, by simulating addressing of the lower-class central processing unit.
2. Description of the Prior Art
An addressing scheme in which data is referred to by using a register as a pointer is called indirect addressing. When indirect addressing using a register (hereinafter, referred to as register indirect addressing) is performed in a central processing unit (hereinafter, referred to as a CPU) 1 equipped with a 16-bit general-purpose register W.sub.0, addresses 0000h-FFFFh in a memory are accessible, that is, a memory area of 64 kbytes (=2.sup.16) is available. Any address (for example, the address "1234h") has a 16-bit notation in this scheme. When such an address is stored in the above-mentioned 16-bit general purpose register W.sub.0, addressing using the general purpose register W.sub.0 as a pointer is made possible.
One of the methods for expanding an accessible area in a memory is known as a bank addressing. In bank addressing, lower bits of address data are stored in the general purpose register W.sub.0, and higher bits of address data are stored in a data bank register DBR. According to this scheme, any address is represented using data in the data bank register DBR and data in the general purpose register W.sub.0 (see Japanese Laid-Open Patent Applications No.64-91254, No.62-89294, No. 51-132047, No.1-92851 and No.3-204029).
A description will now be given of register indirect addressing using the bank addressing. It is assumed that an address having a size exceeding the size (16 bits) of the general purpose register W.sub.0 is given. If we take an example of "123456h", the lower portion which fits the 16-bit notation, that is, "3456h" is stored in the 16-bit general purpose register W.sub.0, and the higher 8-bit portion "12h" is stored in the data bank register DBR. A command may specify the general purpose register W.sub.0 holding the lower 16-bit address portion while at the same causing the data bank register DBR to output the higher 8-bit data. Given that the data bank register DBR has a 8-bit capacity and the general purpose register Wo has a 16-bit capacity, a memory area representable by a 24-bit (8+16) notation is accessible. That is, a memory area as large 16 megabytes (=2.sup.24) is available.
When the register indirect addressing is performed in a CPU 2 equipped with a 32-bit general-purpose register W.sub.1, it is possible to access a memory area exceeding the 64-kilobyte limitation without using the data bank register DBR. That is, the aforementioned exemplary address "123456h" is stored as it is in the 32-bit general purpose register W.sub.1 so that the bank register DBR is not necessary.
In case that the CPU 2 is an downward compatible model for the CPU 1, that is, in case the CPU 2 is capable of executing programs written for the CPU 1, but the CPU 1 is not necessarily capable of executing programs written for the CPU 2, the CPU 2 is expected to execute programs written for the CPU 1. Hence, the data bank register DBR is included in a programming model for the CPU 2. Accordingly, it is necessary for the CPU 2 to be adapted for register indirect addressing using the data bank register DBR.
It is conceivable that both the indirectly addressing using a 16-bit register and the indirect addressing using a 32-bit register are provided in the CPU 2. However, such an arrangement increases the number of indirect addressing schemes used, in proportion to the number of registers used (more specifically, a range of register IDs specified). An increase in the number of addressing schemes produces disadvantages such as an increase in a command code length and a decrease in the number of command types.